make, the GNU recompiling tool, determines automatically which pieces of a large program you need to recompile and then issues commands to recompile them. make conforms to IEEE Standard 1003.2-1992 (POSIX.2) and is compatible with any programming language whose compiler can run with command line input from a shell. make is not limited only to building programs; it can be used for any task in which some files must update automatically whenever associated files change.
To use make, you must write a file (a makefile) that describes the relationships among files in your program and provides commands for updating each file. In a program, typically, the executable file is updated from object files, which are in turn made by compiling source files.
When using make to recompile an executable, the result may change source files in a directory. If you changed a header file, to be safe, you must recompile each source file that includes that header file. Each compilation produces an object file corresponding to the source file. If any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable.
make uses the makefile database and the last modified files to decide which of the other files needs updating. For each of those files, make implements the commands recorded in the data base of the makefile. The makefile has rules which explain how and when to remake certain files that are the targets of a particular rule. A simple makefile rule has the following form:
target... : dependency... command |
target is usually the name of a file that a program generates; examples of targets are executable or object files. A target can also be the name of an action to carry out, such as with the clean command (a command that, deletes all files from a build directory before building). A dependency is a file that is used as input to create the target. A target often depends on several files. command is activated by make wnen dependancy has changed. A rule may have more than one command, with each command on its own line. Usually a command is in a rule with dependencies and serves to create a target file if any dependencies change. However, the rule that specifies commands for the target does not require dependencies; for instance, the rule containing the delete command that associates with the target, clean, does not have dependencies. make activates commands on the dependencies to create or to update the target. A rule can also explain how and when to activate a command. A makefile can contain other text besides rules; a simple makefile requires only rules. Rules generally follow the same pattern.
Note that every command line in a makefile must begin with a tab character.
edit : main.o kbd.o command.o display.o insert.o search.o \
files.o utils.o
cc -o edit main.o kbd.o command.o display.o insert.o \
search.o files.o utils.o
main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
command.o : command.c defs.h command.h
cc -c command.c
display.o : display.c defs.h buffer.h
cc -c display.c
insert.o : insert.c defs.h buffer.h
cc -c insert.c
search.o : search.c defs.h buffer.h
cc -c search.c
files.o : files.c defs.h buffer.h command.h
cc -c files.c
utils.o : utils.c defs.h
cc -c utils.c
clean :
rm edit main.o kbd.o command.o display.o insert.o \
search.o files.o utils.o
|
The targets in the example makefile include the executable file, edit, and the main.o and kbd.o object files. main.c and defs.h are the dependency files. Each .o file is both a target and a dependency. When a target is a file, it needs to be recompiled or relinked if any of its dependencies change. You must first update any dependencies that automatically generate. In the example Makefile, edit depends on eight object files; the object file, main.o, depends on the source file, main.c, and on the defs.h header file. A shell command follows each line that contains a target and dependencies, saying how to update the target file; a tab character must come at the beginning of every command line to distinguish command lines from other lines in the makefile. make does not know anything about how the commands work; it is up to you to supply commands that update the target file properly. All make does is execute the commands in the rule you have specified when the target file needs updating.
For more details, refer to Using make.